DOI

  • A. Vandooren
  • J. Franco
  • Z. Wu
  • L. Witters
  • A. Walke
  • W. Li
  • V. Deshpande
  • F. M. Bufler
  • N. Rassoul
  • G. Hellings
  • G. Jamieson
  • F. Inoue
  • G. Verbinnen
  • K. Devriendt
  • N. Heylen
  • E. Vecchio
  • T. Zheng
  • W. Vanherle
  • A. Hikavyy
  • B. T. Chan
  • R. Ritzenthaler
  • G. Besnard
  • W. Schwarzenbach
  • G. Gaudin
  • I. Radu
  • B. Y. Nguyen
  • N. Waldron
  • V. De Heyn
  • D. Mocuta
  • N. Collaert

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V G= V th+ 0.6 V, 125 °C), even without the use of 'reliability' anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

Original languageEnglish
Article number8487028
Pages (from-to)5165-5171
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume65
Issue number11
DOIs
Publication statusPublished - Nov 2018

    Research areas

  • 3-D sequential, analog, Annealing, Bonding, Doping, junctionless (JL) devices, Logic gates, low-temperature CMOS, matching, MOS devices, Reliability, RF, Silicon, silicon-on-insulator (SOI), wafer bonding.

ID: 40026283