1. 2004
  2. An 8Gb/s Capacitive-Coupled Receiver with High Common-Mode Rejection for Un-Coded Data

    Maillard, X. & Kuijk, M., 1 Nov 2004, In : IEEE JOURNAL OF SOLID-STATE CIRCUITS. 39, 11, p. 1909-1915 7 p.

    Research output: Contribution to journalArticle

  3. An 8-Gb/s Capacitive Coupled Receiver with High Common-Mode Rejection for Un-coded Data

    Maillard, X. & Kuijk, M., 15 Feb 2004, 2004 IEEE International Solid-State Circuits Conference. ISSCC, Vol. 1, pp. 242-243, San fransico, US., p. 242-243 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference paper

  4. 2002
  5. A 900-Mbit/s CMOS Data Recovery DLL using Half-Frequency Clock

    Maillard, X., Kuijk, M. & Devisch, F., 1 Jun 2002, In : IEEE JOURNAL OF SOLID-STATE CIRCUITS. 37, p. 711-715 5 p.

    Research output: Contribution to journalArticle

  6. Half-conductive coupling interconnection technology for digital transmission between CMOS chips

    Devisch, F., Maillard, X., Pan, W., De Tandt, C., Vounckx, R. & Kuijk, M., 1 Feb 2002, In : IEEE Transactions on Advanced Packaging. 1, p. 97 1 p.

    Research output: Contribution to journalArticle

  7. 2001
  8. A 900 Mib/s CMOS Data Recovery DLL using Half-Frequency Clock

    Maillard, X., Devisch, F. & Kuijk, M., 2001, IEEE/LEOS. IEEE/LEOS , Vol. 1, pp. 81-84, Benelux., p. 84 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference paper

  9. Low power LVDS receiver with high common mode rejection

    Maillard, X., Devisch, F. & Kuijk, M., 2001, European Conference on Circuit Theory and Design. European Conference on Circuit Theory and Design, Vol. 3, pp. 321-324., p. 324 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference paper

ID: 53313